Energy storage and hold-up method and apparatus for high density power conversion

ABSTRACT

A method and apparatus for adaptively configuring an array of voltage transformation modules is disclosed. The aggregate voltage transformation ratio of the adaptive array is adjusted to digitally regulate the output voltage for a wide range of input voltages. An integrated adaptive array having a plurality of input cells, a plurality of output cells, or a plurality of both is also disclosed. The input and output cells may be adaptively configured to provide an adjustable transformer turns ratio for the adaptive array or in the case of an integrated VTM, an adjustable voltage transformation ratio for the integrated VTM. A controller is used to configure the cells and provide digital regulation of the output. A converter having input cells configured as a complementary pair, which are switched out of phase, reduces common mode current and noise. Series connected input cells are used for reducing primary switch voltage ratings in a converter and enabling increased operating frequency or efficiency. An off-line auto-ranging power supply topology is disclosed. An auto-ranging converter module (“ACM”) includes 2 or more input cells magnetically coupled to an output cell providing auto-ranging, isolation, and voltage transformation. The ACM converts a rectified line voltage to a low DC bus voltage. The topology allows regulation and power factor correction to be provided at a low voltage increasing energy density and efficiency and reducing cost. A fully integrated PCM may also include a hold-up circuit, a DC input, and a power regulator with or without power factor correction. A PCM with PFC may combine the hold-up and smoothing capacitors for further increases in power density.

This application is a divisional of U.S. application Ser. No.11/110,091, filed Apr. 19, 2005, now U.S. Pat. No. 7,408,795, which is acontinuation-in-part of U.S. application Ser. No. 10/959,779, filed Oct.6, 2004, now U.S. Pat. No. 7,212,419, which is a continuation-in-part ofU.S. application Ser. No. 10/785,465, filed Feb. 24, 2004, now U.S. Pat.No. 7,170,764. U.S. application Ser. Nos. 11/110,091, 10/959,779 and10/785,465 are all incorporated herein by reference.

TECHNICAL FIELD

This invention relates to the field of electrical power conversion andmore particularly to regulated power conversion systems and off-lineauto-ranging power supplies.

BACKGROUND

DC-DC converters transfer power from a DC electrical input source to aload by transferring energy between windings of an isolationtransformer. The DC output voltage delivered to the load is controlledby adjusting the timing of internal power switching elements (e.g., bycontrolling the converter switching frequency and/or the switch dutycycle and/or the phase of switches). As defined herein, the functions ofa “DC-DC converter” comprise: a) isolation between the input source andthe load; b) conversion of an input voltage to an output voltage; and c)regulation of the output voltage. DC-DC converters may be viewed as asubset of a broad class of switching power converters, referred to as“switching regulators,” which convert power from an input source to aload by processing energy through intermediate storage in reactiveelements. As defined herein, the functions of a “Switching Regulator”comprise: a) conversion of an input voltage to an output voltage, and b)regulation of the output voltage. If the required output voltage isessentially a positive or negative integer (or rational) multiple of theinput voltage, the conversion function may also be efficiently performedby a capacitive “Charge Pump,” which transfers energy by adding andsubtracting charge from capacitors.

Vinciarelli et al, “Efficient Power Conversion” U.S. Pat. No. 5,786,992disclose expanding the operating voltage range of isolated DC-DCconverters by connecting their inputs and/or outputs in series.

Non-resonant full-bridge, half-bridge, and push-pull DC-to-DCtransformer topologies are known. See e.g., Severns and Bloom, “ModernDC-to-DC Switchmode Power Conversion Circuits,” ISBN 0-442-21396-4, pp.78-111. Series, parallel, and other resonant forms of switching powerconverters are also known. See e.g., Steigerwald, “A Comparison ofHalf-Bridge Resonant Converter Topologies,” IEEE Transactions on PowerElectronics, Vol. 2, No. 2, April, 1988. Variable frequency, seriesresonant, half-bridge converters for operation from an input voltagesource are described in Baker, “High Frequency Power Conversion WithFET-Controlled Resonant Charge Transfer,” PCI Proceedings, April 1983,and in Nerone, U.S. Pat. No. 4,648,017. Half-bridge, single-stage, ZVS,multi-resonant, variable frequency converters, which operate from aninput voltage source are shown in Tabisz et al, U.S. Pat. No. 4,841,220and Tabisz et al, U.S. Pat. No. 4,860,184. A variable frequency,full-bridge, resonant converter, in which an inductor is interposedbetween the input source and the resonant converter is described inDivan, “Design Considerations for Very High Frequency Resonant ModeDC/DC Converters,” IEEE Transactions on Power Electronics, Vol. PE-2,No. 1, January, 1987. A variable frequency, ZVS, half-bridge LLC seriesresonant converter is described in Bo Yang et al, “LLC ResonantConverter for Front End DC-DC Conversion,” CPES Seminar 2001,Blacksburg, Va., April 2001. Analysis and simulation of a “Low Q”half-bridge series resonant converter, wherein the term “Low Q” refersto operation at light load, is described in Bo Yang et al, “Low QCharacteristic of Series Resonant Converter and Its Application,” CPESSeminar 2001, Blacksburg, Va., April 2001.

Fixed-frequency half-bridge and full-bridge resonant converters are alsoknown in which output voltage control is achieved by controlling therelative timing of switches. A half-bridge, single-stage, ZVS,multi-resonant, fixed-frequency converter that operates from an inputvoltage source is shown in Jovanovic et al, U.S. Pat. No. 4,931,716. Afull-bridge, single-stage, ZVS, resonant, fixed-frequency converter thatoperates from an input voltage source is shown in Henze et al, U.S. Pat.No. 4,855,888.

A full-bridge, single-stage, ZCS, series-resonant, fixed-frequencyconverter, operating at a frequency equal to the characteristic resonantfrequency of the converter, is shown in Palz, “Stromversorgung vonSatelliten—Wanderfeldrohren hoher Leistung” (“Power Supply forSatellites—High Capacity Traveling-Wave Tubes”), Siemens Zeitschrift,Vol. 48, 1974, pp. 840-846. Half and full-bridge, single-stage, ZVS,resonant, converters, for powering fluorescent tubes are shown inNalbant, U.S. Pat. No. 5,615,093.

A DC-to-DC Transformer offered for sale by SynQor, Hudson, Mass., USA,called a “BusQor™ Bus Converter,” that converts a regulated 48 VDC inputto a 12 VDC output at a power level of 240 Watts and that can beparalleled with other similar converters for increased output powerdelivery, and that is packaged in a quarter brick format, is describedin data sheet “Preliminary Tech Spec, Narrow Input, Isolated DC/DC BusConverter,” SynQor Document No. 005-2BQ512J, Rev. 7, August, 2002.

The art of resonant power conversion, including operation below or aboveresonant frequency, utilizing either ZCS or ZVS control techniques andallowing the resonant cycle to be either completed or purposelyinterrupted, is summarized in Chapter 19 of Erickson and Maksimovic,“Fundamentals of Power Electronics,” 2nd Edition, Kluwer AcademicPublishers, 2001.

Cascaded converters, in which a first converter is controlled togenerate a voltage or current, which serves as the source of input powerfor a DC-to-DC transformer stage, are known. A discussion of canonicalforms of cascaded converters is given in Severns and Bloom, ibid, at,e.g., pp. 114-117, 136-139. Baker, ibid, discusses the use of a voltagepre-regulator cascaded with a half-bridge, resonant, variable-frequencyconverter. Jones, U.S. Pat. No. 4,533,986 shows a continuous-mode PWMboost converter cascaded with both PWM converters and FM resonanthalf-bridge converters for improving holdup time and improving the powerfactor presented to an AC input source. A zero-voltage transition,current-fed, full-bridge PWM converter, comprising a PWM boost converterdelivering a controlled current to a PWM, full-bridge converter, isshown in Hua et al, “Novel Zero-Voltage Transition PWM Converters,” IEEETransactions on Power Electronics, Vol. 9, No. 2, March, 1994, p. 605.Stuart, U.S. Pat. No. 4,853,832, shows a full-bridge series-resonantconverter cascaded with a series-resonant DC-to-DC transformer stage forproviding AC bus power to distributed rectified loads. A half-bridge PWMDC-to-DC transformer stage for use in providing input power topoint-of-load DC-DC converters in a DPA is described in Mweene et al, “AHigh-Efficiency 1.5 kW, 390-50V Half-Bridge Converter Operated at 100%Duty Ratio,” APEC '92 Conference Proceedings, 1992, pp. 723-730.Schlecht, U.S. Pat. Nos. 5,999,417 and 6,222,742 shows DC-DC converterswhich incorporate a DC-to-DC transformer stage cascaded with a switchingregulator. Vinciarelli, “Buck-Boost DC-DC Switching Power Conversion,”U.S. patent application Ser. No. 10/214,859, filed Aug. 8, 2002,assigned to the same assignee as this application and incorporated byreference, discloses a new, high efficiency, ZVS buck-boost convertertopology and shows a front-end converter comprising the disclosedtopology cascaded with a DC-DC converter and a DC-to-DC transformer.

In one aspect, prior art approaches to off-line power conversion may becharacterized by how they accommodate a broad range of nominal linevoltages, e.g., 110 VAC (i.e. 85-120 VAC) and 220 AC (i.e. 170-240 VAC).In one approach, the line is simply rectified and power conversioncircuitry is designed to operate over the full range of variation of therectified line voltage; in another approach, called “auto-ranging”, therectification circuitry is reconfigured based upon the nominal value ofthe line voltage and the range of voltages over which power conversioncircuitry must operate is reduced. In another aspect, off-line powerconversion may be characterized in terms of whether or not power factorcorrection (“PFC”) is provided. Auto ranging is commonly provided innon-PFC power supplies using a capacitive voltage doubler. Referring toFIG. 10 for example, an off-line power supply includes a bridgerectifier 501, capacitors 502 and 503 connected in series across therectifier output, and a doubler switch 506 which may be manually orautomatically controlled for effecting voltage doubling. For high linevoltages e.g. 220 VAC the switch remains open and the rectified voltageV₂ will approximately equal the peak input voltage V_(IN). For low lineapplications, the switch 506 is closed and V₂ will approximately equaltwice the peak input voltage V_(IN)and the voltage V₂ will remainnominally at 220V regardless of whether a 110 or 220 VAC line isconnected at the input. The DC-DC converter 504 provides the voltagetransformation, isolation and regulation functions for power deliveredto the load 505.

Because it requires the use of energy storage capacitors at the outputof the rectifiers, the capacitive voltage-doubler is not generallysuitable for use in PFC applications. Vinciarelli et al., “PassiveControl of Harmonic Current Drawn From an AC Input by RectificationCircuitry,” U.S. Pat. No. 6,608,770, issued Aug. 19, 2003, assigned tothe same assignee as this application and incorporated by reference,discloses capacitive voltage-doubling auto-ranging circuitry whichpassively controls the harmonic current drawn from an AC line.

Another auto-ranging approach suitable for both PFC and non-PFCapplications is the use of a line frequency transformer with switchedwindings. The line voltage may be applied across all or part of theprimary winding depending on the applied line voltage. In PFCapplications the more common approach is use of a PFC boost converter asshown in FIG. 11. The off-line auto-ranging PFC power supply of FIG. 11includes bridge rectifier 501, non-isolated PFC Boost converter 507, andstorage capacitor 508, followed by isolated DC-DC converter 504. Inorder to control the current drawn from the AC line for PFC, the outputvoltage VB of the boost converter must be set to a voltage greater thanthe highest peak input voltage V_(IN). In a typical power supplydesigned for international use, the boost voltage may be 400V. Power isthen converted from the boost voltage down to the load voltage by DC-DCconverter 504, which provides voltage transformation, regulation, andisolation. Operation of the boost and DC-DC converters at such highvoltages includes cost and performance penalties including, lower figureof merit for switches at high voltages and safety issues for energystorage at high voltages.

One solution, disclosed in Vinciarelli et al., “Efficient PowerConversion,” U.S. Pat. No. 5,786,992, issued Jul. 28, 1998, assigned tothe same assignee as this application and incorporated by reference,configures power converters in series and parallel allowing thecombination of converters to operate over a greater voltage range.

SUMMARY

In general, one aspect features a method of converting power a method ofconverting power from a source at a source voltage for delivery to aload at a load voltage where the source voltage may vary between a highline voltage and a low line voltage in a normal operating range. Themethod provides DC-DC voltage transformation and isolation in a firstpower conversion stage. The first stage has a CA input for receivingpower from the source and a CA output. Power regulation is provided in asecond power conversion stage. The second stage includes a PR input forreceiving power from the CA output of the first stage, regulationcircuitry, and a PR output for delivering power to the load. Theregulation circuitry is adapted to maintain the load voltage within aregulation range while the PR input voltage remains within a normaloperating range. A hold-up circuit is provided with a charge path and adischarge path for connection to a hold-up capacitance. The dischargepath provides a low impedance connection between the hold-up capacitanceand the PR input for supplying power to the power regulator. The chargepath provides a charge current to charge the hold-up capacitance. Thehold-up circuit is configured to charge the hold-up capacitance when afirst predetermined condition is satisfied and to provide power to thePR input when a second predetermined condition is satisfied.

Implementations of the method may include one or more of the followingfeatures.

The DC-DC voltage transformation and isolation may include an integratedadaptive converter array having a first input cell and a second inputcell, each input cell having a respective number, P_(x), of turns, anoutput cell having a respective number, S_(x), of turns and magneticcoupling between the turns to form a transformer common to the first andsecond input cells and the output cell. The input cells may beconfigured in a parallel connection for operation at the low linevoltage and in a series connection for operation at the high linevoltage.

The DC-DC voltage transformation and isolation may include an array oftwo or more VTMs, each VTM having an input, an output, and asubstantially fixed voltage transformation ratio, K=V_(out)/V_(in), overthe normal operating range, where V_(in) is the voltage across therespective VTM input and V_(out) is the voltage across the respectiveVTM output, and providing isolation between its input and its output.The inputs of the VTMs may be configured in a parallel connection foroperation at the low line voltage and in a series connection foroperation at the high line voltage.

Circuitry may be provided for performing the method in a self-containedassembly for installation as a unit having terminals for connecting tothe CA input, the PR output, and the hold-up circuit. The hold-upcapacitor may be provided as a component external to the assembly.Control circuitry adapted to detect the first and second predeterminedconditions and to configure the hold-up circuit may be provided. Thecontrol circuitry may be adapted to detect an error signal from theregulation circuitry and the second predetermined condition may comprisethe error signal being outside a predetermined range. The secondpredetermined condition may comprise the source voltage being below afirst predetermined level and the hold-up capacitor being charged abovea second predetermined level. A DC input directly coupled to the secondpower conversion stage may be provided for receiving power from anexternal DC source. The DC input may be connected to the PR input viathe discharge path. The DC input may be connected to the PR input viaswitch circuitry capable of blocking current flow in both directionswhen OFF and conducting current in both directions when ON. The switchcircuitry may be turned ON to connect the external DC source to the PRinput. The hold-up circuit may include switch circuitry capable ofblocking current flow in both directions when OFF and conducting currentin both directions when ON. The switch circuitry may be controlled toprovide the charge path and the discharge path. A switch may be providedin the discharge path for connecting the hold-up capacitance to the PRinput when the switch is ON. The hold-up circuit may include a currentlimiting element in the charge path. Power factor correction may beprovided in the power regulator and a smoothing capacitance may beprovided at the PR output. A boost circuit may be provided with anoutput connected to charge the hold-up capacitance. The boost circuitmay have an input connected to the PR output. Circuitry to switch asingle capacitance between a first configuration and a secondconfiguration may be provided so the capacitance may be connected to thePR output as the smoothing capacitance in the first configuration and tothe hold-up circuit as the hold-up capacitance in the secondconfiguration.

In general, one aspect features a method of converting power from an ACsource for delivery to a system including a load. The method provides apower converter module (“PCM”) having input terminals for receivingpower from the source, output terminals for delivering power to a loadat a regulated DC voltage, and power conversion circuitry. The PCM is aself-contained assembly adapted to be installed as a unit. The powerconversion circuitry comprises DC-DC voltage transformation (“VT”)circuitry and power regulation (“PR”) circuitry. The VT circuitry has aninput connected to the input terminals, an output for delivering powerto the PR circuitry, and provides voltage transformation and isolation.The PR circuitry has an output connected to the output terminals andprovides output regulation. A capacitive energy storage componentexternal to the PCM is provided for the isolated side of the powerconversion circuitry.

Implementations of the method may include one or more of the followingfeatures.

The VT circuitry may include an integrated adaptive converter arrayhaving a first input cell and a second input cell, each input cellhaving a respective number, P_(x), of turns, an output cell having arespective number, S_(x), of turns, and magnetic coupling between theturns to form a transformer common to the first and second input cellsand the output cell. Control circuitry may be provided for configuringthe input cells in a parallel connection for operation at a low linevoltage and in a series connection for operation at a high line voltage.The VT circuitry may include an array of two or more VTMs, each VTMhaving an input, an output, and a substantially fixed voltagetransformation ratio, K=V_(out)/V_(in), over the normal operating range,where V_(in) is the voltage across the respective VTM input and V_(out)is the voltage across the respective VTM output, and providing isolationbetween its input and its output. Control circuitry may be provided forconfiguring the VTMs in a parallel connection for operation at a lowline voltage and in a series connection for operation at a high linevoltage. The PR circuitry may include a buck-boost converter with PFCcircuitry. The power conversion circuitry may include a hold-up switchconnected between a hold-up terminal and the PR input and a smoothingswitch connected between the hold-up terminal and the PR output. The PRcircuitry may include power factor correction circuitry and the PCM mayrequire a single external capacitive energy storage component connectedto the hold-up terminal. The power conversion circuitry may include ahold-up switch connected between a hold-up terminal and the PR input andthe capacitive energy storage component may be connected to the hold-upterminal to provide power to the PR input. The PR circuitry may includepower factor correction circuitry and the external capacitive energystorage component may be connected to PR output as a smoothingcapacitor.

The details of one or more embodiments of the invention are set forth inthe accompanying drawings and the description below. Other features,objects, and advantages of the invention will be apparent from thedescription and drawings, and from the claims.

DESCRIPTION OF DRAWINGS

FIG. 1 shows an input-switched adaptive array of VTMs.

FIG. 2 shows an output-switched adaptive array of VTMs.

FIG. 3 shows a schematic diagram of a full-bridge SAC.

FIG. 4 shows a schematic diagram of a modified SAC with an adaptivearray of input cells integrated with a common output circuit.

FIGS. 5A and 5B show use of a linear regulator with an adaptive array ofVTMs.

FIG. 6 shows a schematic diagram of an array of VTM cells with theinputs and outputs adaptively configured in series to provide outputregulation.

FIG. 7 shows a schematic of an output switched adaptive array of VTMs.

FIG. 8 shows a converter topology using a complementary pair of inputcells.

FIG. 9 shows an off line auto-ranging converter module topology withcomplementary half-bridge SAC input cells.

FIG. 10 shows a prior art off-line auto-ranging power supply.

FIG. 11 shows a prior art off-line auto-ranging power supply with powerfactor correction.

FIG. 12 shows an off-line auto-ranging power supply using anauto-ranging converter module cascaded with a power factor correctedpower regulator module.

FIG. 13 shows an off-line auto-ranging power supply using auto-rangingconverter modules cascaded with a power regulator module for use with athree-phase line.

FIG. 14 shows an off-line auto-ranging power supply having an integratedauto-ranging converter module, low line hold-up circuit, andpower-factor-correcting power-regulator module.

FIG. 15 shows an off-line auto-ranging power supply having an integratedauto-ranging converter module, low line hold-up circuit with boostconverter, and power-factor-correcting power-regulator module.

FIG. 16 shows an off-line auto-ranging power supply having an integratedauto-ranging converter module and non-power factor correcting powerregulator module.

FIG. 17 shows an alternate hold-up circuit for use in power factorcorrecting and non-power factor correcting topologies.

FIG. 18 shows an alternate hold-up circuit for use in power factorcorrecting topologies.

FIG. 19A shows a top view of a power converter module.

FIG. 19B shows a side view of a power converter module.

FIG. 19C shows an exploded perspective view of a power converter module.

FIG. 19D shows a side assembly view of a power converter module.

Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

A Voltage Transformation Module (“VTM”) as defined herein delivers a DCoutput voltage, V_(out), which is a fixed fraction of the voltage,V_(in), delivered to its input and provides isolation between its inputand its output. The voltage transformation ratio or voltage gain of theVTM (defined herein as the ratio, K=V_(out)/V_(in), of its outputvoltage to its input voltage at a load current) is fixed by design, e.g.by the VTM converter topology, its timing architecture, and the turnsratio of the transformer included within it. Vinciarelli, “FactorizedPower Architecture With Point Of Load Sine Amplitude Converters,” U.S.patent application Ser. No. 10/264,327, filed Oct. 1, 2002, (referred toherein as the “Factorized Application”) assigned to the same assignee asthis application and incorporated by reference, discloses preferredconverter topologies and timing architectures for VTMs, which will begenerally referred to as a Sine Amplitude Converter (“SAC”) topology.

The SAC topology has many advantages over prior art DC-to-DC transformertopologies. The SAC topology may incorporate a “low Q” resonant tank(where the term “low Q” has the meaning given in the FactorizedApplication with respect to transformers for use in a SAC) and isnominally operated at resonance so that the reactive impedances of theelements of the resonant tank cancel each other out. The SAC uses aresonant topology at resonance so that the impedance of the resonantcircuit becomes essentially resistive, minimizing the output impedanceand open-loop resistance of the converter, and thus minimizing open-loopvoltage droop as a function of changing load. Greater consistency inopen-loop DC output resistance, owing to the elimination of dependencyon reactive impedances, gives rise to fault tolerant power sharingattributes which are particularly desirable in applications in whichmultiple, paralleled, VTMs are operated as a power sharing array.

Operating waveforms in SAC converters closely approximate puresinusoidal waveforms, thus optimizing spectral purity, and hence theconverter's conducted and radiated noise characteristics. In operation,a SAC maintains an essentially constant conversion ratio and operatingfrequency as the amplitudes of its essentially sinusoidal voltage andcurrent waveforms vary in response to a varying output load. The timingarchitecture of the SAC topology supports ZVS operation of the primaryswitches and ZCS and ZVS operation of the secondary switches, virtuallyeliminating switching losses in the primary switching elements andsecondary switching elements, or rectifiers, particularly synchronousrectifiers, enabling higher switching frequencies and higher converterpower density and efficiency. Sine Amplitude Converters provide the bestcombination of attributes to support the requirements of VTMs and highperformance DC-DC converters.

VTMs and in particular SACs are capable of achieving very high powerdensities. The present application discloses methods and apparatus foradaptively configuring an array of VTMs, as the input voltage to thearray of VTMs varies over a pre-defined range, in order to regulate theoutput voltage of the array.

A “digital” ladder array of VTMs 100 adaptively configurable to providea regulated output voltage from an input source 10 is shown in FIG. 1.The adaptive VTM array 100 adjusts to changes in input voltage orchanging output voltage requirements by selectively configuring theVTMs. The VTM outputs are connected in parallel to supply power to theload 20. Each VTM has a transformation ratio, K, selected to provide thenecessary resolution. In the example of FIG. 1, VTMs 101, 102, 103, 104,and 105 have transformation ratios of 1/16, 1/8, 1/4, 1/2, and 1/1,respectively for a digital ladder (thus the reference to the array as a“digital” array). The VTM inputs are connected to receive power from theinput source through controlled switches 110-119 which may be lowresistance (FET) switches. The array 100 of FIG. 1 may be configured foran aggregate transformation ration of 1/1 to 1/31 in steps of 1 in thedenominator by switching the VTM inputs in and out of the input circuit.A VTM is disconnected in FIG. 1 by closing its respective shunt switch(110-114) and opening its respective series switch (115-119). The VTMsthat are disconnected may be disabled (i.e., rendered non-operating)until switched back into the circuit or may remain enabled. A ladderswitch controller 106 senses the input voltage and configures the ladderswitches to provide the necessary aggregate voltage transformation ratioto regulate the load voltage. The controller 106 may also sense the loador array output voltage as shown in FIG. 1.

The input voltage will divide across the series connected inputs of VTMshaving their outputs connected in parallel in proportion to theirrespective individual transformation ratios. The voltage across theinput of VTM_(n) (in a series-connected-input andparallel-connected-output array) may be expressed as follows:

$V_{i_{n}} = {\frac{V_{Source}}{K_{n}} \times K_{aggr}}$where K_(aggr), the aggregate transformation ratio for theseries-connected-input and parallel-connected-output array of VTMs, isthe reciprocal of the sum of the individual transformation ratios ofthose VTMs that are connected in the array:

$K_{aggr} = {1/{\sum\limits_{connected}\;\frac{1}{K_{i}}}}$

Referring to the example of FIG. 1, assume that the array 100 is todeliver a nominal 2.3V to the load 20 from an input source 10 that mayvary from 36V to 72V. At low line conditions with Vin=36V, thecontroller configures the switches (110, 116-119 open and 115, 111-114closed) so that only the input of VTM 101 is connected across the inputsource and the other VTMs 102-105 are disconnected from the source.Since the only connected VTM is the one having K₁=1/16, the aggregatetransformation ratio will be K_(aggr)=1/16 and the array will deliverV_(out)=V_(Source) K_(aggr)=36/16=2.25V to the load. As the sourcevoltage increases, the controller adaptively reconfigures the array toprovide the necessary load regulation. For example, for a source voltageof 38V, the controller may reconfigure the array by connecting theinputs of VTMs 101 and 105 in series and disconnecting VTMs 102-104(switches 110, 114, 116-118 open, 111-113, 115, 119 closed) to providean aggregate transformation ratio K_(aggr)=1/(16+1)=1/17 and an outputvoltage V_(out)=V_(Source) K_(aggr)=38/17=2.24V. At maximum inputvoltage, with Vin=72V, controller 106 configures the switches (110-114open, 115-119 closed) to connect all of the VTMs in series. Theaggregate transformation ratio will be K_(aggr)=1/(16+8+4+2+1)=1/31 andthe array will deliver 72/31=2.32V to the load.

It will be appreciated that the adaptive digital ladder VTM array ofFIG. 1 efficiently provides all of the classic functions of a DC-DCconverter (including isolation, voltage step-up or step down, ANDregulation) by adaptively configuring a series combination of VTM inputsto adjust the aggregate K factor, K_(aggr). The number of VTMs in thearray may be increased to provide greater resolution and thus betterregulation. For example, an additional VTM (e.g., one having atransformation ratio K=2/1 or one having a transformation ratio K=1/32)may be added to further increase the resolution or the input range ofthe array. However, the minimum input or output operating voltage of theVTMs may impose a practical limitation on the resolution in the K, 2K,4K digital ladder array of FIG. 1 because of practical limitations inachievable values of K in a VTM.

If the output voltage regulation requirement exceeds the resolution ofan adaptive VTM array, finer regulation may be provided by an analogdissipative linear regulator in series with the input or output of a VTMarray. FIGS. 5A and 5B, show a linear regulator 107 in series with theoutput and input, respectively, of adaptive array 100. If, for example,an adaptive VTM array can achieve a regulation resolution of 1 percentwith a manageable number of bits, the dissipation associated with usingan appropriately designed analog series linear regulator, e.g. 107, toabsorb substantially all of the 1% VTM array error may be negligible interms of the overall converter efficiency. In fact such a loss may besmaller than the loss associated with a series-connected switchingregulator (e.g., a “PRM”, as described in the Factorized Application,and that may, in some applications, use the topology described inVinciarelli, “Buck-Boost DC-DC Switching Power Conversion,” U.S. Pat.No. 6,788,033 issued Sep. 7, 2004 (referred to herein as the “Buck-BoostPatent”), both assigned to the same assignee as this application andincorporated by reference). Use of a series linear regulator alsoeliminates the response delays and switching noise that would beintroduced by use of a series-connected switching regulator. The analogseries linear regulator also may provide enough bandwidth to effectivelyfilter “hash” or “digital jitter” that may be generated due to instancesof reconfiguration of the array.

It may be preferable to provide the configuration switches on the highervoltage side of the array to reduce power dissipation in the switches.In the example of FIG. 1, the source voltage was stepped down by thearray; therefore, the switches were placed on the input side of thearray. In voltage step-up applications, the switches may be placed onthe secondary side to produce a series connected secondary adaptivearray.

Referring to FIG. 2, an example of a step-up adaptive array 150 withconfiguration switches 161-164, 166-169 on the output side of the arrayis shown. The array 150 is designed to provide 48+/−1 Volt output froman input voltage range of 10-15V. For this application, the array mustprovide a minimum transformation ratio less than or equal to K_(min):

$K_{\min} = {\frac{V_{{out}_{\max}}}{V_{{in}_{\max}}} = {\frac{48 + 1}{15} = 3.26}}$The array must also provide a transformation ratio greater than or equalto K_(max):

$K_{\max} = {\frac{V_{{out}_{\min}}}{V_{{in}_{\min}}} = {\frac{48 - 1}{10} - 4.7}}$In order to satisfy the regulation requirement, the array must have astep size in the transformation ratio less than or equal to ΔK_(max):

${\Delta\; K_{\max}} = {\frac{V_{out}}{V_{{in}_{\max}}} = {\frac{49 - 47}{15} = {.13}}}$Finally, the array must provide a number of steps in the transformationratio greater than or equal to N_(steps):

$N_{steps} = {\frac{K_{\max} - K_{\min}}{\Delta\; K_{\max}} = {\frac{4.7 - 3.26}{.13} = 11.1}}$From the above calculations, a five VTM array will satisfy the designcriteria. A four-bit K, 2K digital ladder having 15 steps will satisfythe N_(steps) requirement. A step size of ΔK=1/8=0.125 is less than andtherefore satisfies the resolution requirement ΔK_(max) and provides anadjustment range N_(steps)×ΔK=15×1/8=1.875 that is greater thanrequired. VTMs 152, 153, 154, and 155 will have the following respectivetransformation ratios K₅=1/8, K₄=1/4, K₃=1/2, and K₂=1. Thetransformation ratio of the main VTM 151 thus may be set to K₁=3 whichwill easily satisfy the minimum requirement, K_(min) and provide anaggregate transformation ratio for the array ranging from 3.0 to 4.875.

The inputs of the VTMs 151-155 are connected in parallel and the outputsare adaptively connected in series as needed to regulate the outputvoltage. Because the main VTM 151 is configured to deliver powercontinuously it does not have a series or shunt switch on its output(the array of FIG. 1 may also be adapted in this way). Auxiliary VTMs152-155 are configured to form the four-bit K, 2K ladder whose switchesare controlled by the ladder switch controller 156. The controller maysense the source and load voltages to better regulate the load voltage.It will be appreciated that array 150 provides 48V+/−2% over an inputvoltage range from 9.6V to 16.3V.

An example of an adaptive array comprising a power sharing sub-array ofVTMs is shown in FIG. 7. The adaptive array 180 is designed to deliver50 VDC+/−5V from an input source that varies from 38 to 55 VDC. A powersharing sub-array 181, comprising VTMs 181A-181E, each having atransformation ratio K=1, supplies most of the power to the load. As theinput voltage drops, the outputs of auxiliary VTMs 182-184, each ofwhich has a transformation ratio of K=1/8, are switched in series withthe output of the main array 181 by ladder switch controller 185. Theaggregate transformation ratio of the adaptive array 180 varies fromK_(aggr)=1 to 1.375 providing the necessary regulation. The auxiliaryVTMs supply only a small fraction of the total power and therefore donot need to be connected in power sharing arrays for this application.

As described in conjunction with FIGS. 1-2 and 7, the adaptive VTM arrayconcept may be realized with a multiplicity of separate VTMs havingindependent isolation transformers and appropriate K factors, with eachsuch VTM separately controlled to operate at a respective switchingfrequency. However, the Sine Amplitude Converter (“SAC”) is particularlywell suited for use in an integrated version of an adaptive VTM array. Afull-bridge SAC of the type described in the Factorized Application isshown in FIG. 3. The SAC includes one primary circuit and one secondarycircuit. The primary circuit comprises transformer primary windingW_(P), in series with resonant capacitance C_(R), and resonantinductance L_(R) (which may have a low Q (where the term “low Q” has themeaning given in the Factorized Application with respect to transformersfor use in a SAC) and may partially or entirely consist of the primaryreflected leakage inductance of the transformer) driven by primaryswitches SW1, SW2, SW3, SW4. The switches SW1, SW2, SW3, SW4, arecontrolled by the switch controller to operate at near resonance withshort energy recycling intervals to provide zero voltage switching. Theoutput circuit, which includes the transformer secondary winding W_(P),coupled to a rectifier circuit and a filter capacitor, supplies power tothe load.

Referring to FIG. 4, an integrated adaptive array 200 using the SACtopology is shown having a plurality of full-bridge SAC input cells 201,202, 203, 204 coupled to a common SAC output cell 208. The input cellsmay be the same as the primary circuit of FIG. 3 with the addition of abypass capacitor, e.g. capacitors 212 and 222, a series switch, e.g.series switches 211, 221, and a shunt switch, e.g. shunt switch 210, 220for each cell. Also the primary windings W_(P1), W_(P2), W_(P3), . . .W_(Pm) may be part of one transformer 205 having a single secondarywinding Ws coupled to the output circuit 208. The number of turns N₁,N₂, N₃, . . . N_(m) in the primary windings may be selected to providethe appropriate transformation ratio for each cell. Using the K, 2Kdigital ladder example of FIG. 1, the integrated adaptive array SAC 200could have five input cells having respectively 16 turns, 8 turns, 4turns, 2 turns and 1 turn. A resonant switch controller 207 common toall of the cells may operate the primary switches SW1-SW4 of all of thecells (and the synchronous rectifiers in the output cells if used) insynchronism.

The input cells are switched in and out of the series combination asrequired to adjust the aggregate transformation ratio and thus regulatethe output voltage as discussed above in connection with FIG. 1. When aninput cell is in the circuit, its series switch e.g. 211, 221 is closedand its shunt switch e.g. 210, 220 is open. Conversely, when an inputcell is switched out of the circuit its series switch e.g. 211, 221 isopen and its shunt switch e.g. 210, 220 is closed. The ladder switchcontroller 205 controls the series and shunt switches of all of thecells. An input cell that is switched out of the circuit may remainactive (i.e., its primary switches continue to operate) which will keepits respective bypass capacitor, e.g. capacitor 212, 222, charged to theappropriate voltage (due to the bi-directional nature of the SACtopology) thereby eliminating in-rush current problems duringreconfiguration of the digital ladder. The ladder switch controller 206may sense the input voltage and optionally may also sense the loadvoltage to configure the input cells. When connected in series, eachinput cell shares in a fraction of the input voltage equal to the numberof its primary winding turns divided by the total number of turns forall of the input cells that are connected in the array (i.e., where theterm “connected” refers to cells whose shunt switches are open and whoseseries switches are closed).

A more elaborate integrated adaptive array 250 may incorporate aplurality of input cells and a plurality of output cells as shown inFIG. 6. In FIG. 6, a series of VTM input cells are adaptively stacked onthe input (by means of primary series switches 315a-315n and primaryshunt switches 310a-310n analogous to, respectively, switches 115-119and 110-114 in FIG. 1) and a series of VTM output cells are adaptivelystacked on the output (by means of secondary series switches 366a-366mand secondary shunt switches 361a-361m analogous to, respectively,switches 166-169 and 161-164 in FIG. 2) to adaptively adjust theeffective VTM K factor. Because a common transformer comprising primarywindings P₁-P_(n) and secondary windings S₁-S_(m), is used for all ofthe cells, any combination of input and output cells may be combined toprovide the requisite transformation ratio. In general, the integratedadaptive array of FIG. 6, provides an aggregate K expressed as:K_(aggr)=(S₁+S₂+ . . . +S_(m))/(P₁+P₂+ . . . +P_(n))

corresponding to a truncated series combination of connected outputcells having S_(x) transformer turns and a truncated series combinationof connected input cells having P_(x) transformer turns, where the term“connected” has the definition given above). As discussed above, theintegrated adaptive array adjusts to changes in input voltage orchanging output voltage requirements by adaptively configuring the inputand/or output cells in series. It will be appreciated that thegeneralized adaptive array of FIG. 6 may be modified to use a singleinput cell with a plurality of output cells (analogous to the VTM arrayof FIG. 2) or alternatively a single output cell with a plurality ofinputs cells (as discussed above in connection with FIG. 4).Furthermore, some cells in such an array may be permanently connectedand not include series and shunt switches.

An integrated adaptive array based upon the SAC converter topology, suchas the arrays shown in FIGS. 4 and 6, may preserve all of the key SACfeatures, including, in particular: a) the benefits of low Q resonanttransformers for efficient high frequency power processing (where theterm “low Q” has the meaning given in the Factorized Application withrespect to transformers for use in a SAC); b) extremely high powerdensity (exceeding or of the order of 1 KW/in³); c) absence of serialenergy storage through an inductor (as required by classic switchingregulators) leading to fast (<<1 microsecond) transient response; d)fast bi-directional power processing leading to effective bypasscapacitance multiplication; and e) low noise performance owing to theZCS/ZVS characteristics of SACs. Additional advantages, such as reducedsize and cost may be realized by integrating the array within a singlepackage using, e.g., the packaging and transformer design and layouttechniques described in the Factorized Application; in Vinciarelli etal, “Power Converter Package and Thermal Management,” U.S. patentapplication Ser. No. 10/303,613, filed Nov. 25, 2002; and inVinciarelli, “Printed Circuit Transformer,” U.S. patent application Ser.No. 10/723,768, filed Nov. 26, 2003, all assigned to the same assigneeas this application and incorporated by reference.

FIG. 8 shows an array 320 comprising two half-bridge input cells 321,322 connected in series to receive power from an input source 340 havinga voltage, V₁. Primary windings 331, 332 (having P₁ and P₂ turnsrespectively) and secondary winding 333 (having P₂ turns) form part of acommon transformer. Each input cell includes a positive-referencedswitch 324, 328 and a negative-referenced switch 326, 330 providingdoubled-ended drive for primary windings 331, 332. The input cells 321,322 are arranged in a pair with the polarity of the primary windingsreversed. The pair of input cells 321, 322 produces opposing flux whendriven by their respective positive-referenced switch 324, 328. Inoperation, the switches in the pair of input cells are operated 180degrees out of phase in synchronism so that switches SW1 324 and SW4 330are closed at essentially the same time (when switches SW2 326 and SW3328 are open) and switches SW2 326 and SW3 328 are closed at essentiallythe same time (when switches SW1 324 and SW4 330 are open).

One benefit of the complementary pair of input cells is that common-modecurrents that would otherwise be capacitively coupled between primarywindings, 331, 332, and secondary winding, 333, as illustrated by theflow of current I_(CM) between primary 340 and secondary 342 grounds inFIG. 8, will be reduced. In illustration, FIG. 8 incorporates severalrepresentative parasitic capacitances, C_(P1) through C_(P4) 334-337.When switches SW2 and SW3 are opened, the rate-of-change of voltageacross parasitic capacitors C_(P1) 334 and C_(P2) 335 will be positiveand the rate-of-change of voltage across parasitic capacitors C_(P3) 336and C_(P4) 337 will be negative and the net flow of current in thecapacitors will tend to cancel. Likewise, the currents in the parasiticcapacitors will also tend to cancel when switches SW1 and SW4 areopened. The net common-mode current, I_(CM), flowing between the primaryand secondary side of the array can be reduced using this arrangement.

Another advantage of the topology of FIG. 8 is that, for a given inputsource 340 voltage, V₁, the use of a pair of input cells allows use ofprimary switches (e.g., switches SW1-SW4, FIG. 8) having a breakdownvoltage rating that is one-half of the rating that would be required ifa single input cell were used. In one aspect, lower voltage primaryswitches (e.g. MOSFETs) may generally have lower levels of energy storedin the parasitic switch capacitances allowing the peak value ofmagnetizing energy to be set to a lower value while still enablingzero-voltage switching. For a given conversion efficiency, a reductionin magnetizing energy and current may enable operation at a higherfrequency leading to higher power density and a smaller size for theconverter. On the other hand, for a given operating frequency, areduction in magnetizing current may provide for higher conversionefficiency. In another aspect, the use of a pair of input cells in placeof a single input cell may allow use of lower cost, higher performanceswitches. For example, in “off-line” applications the input sourcevoltage, V₁, may be 370 VDC. In such applications use of a pair of inputcells enables use of primary switches having a 200 V breakdown rating,in contrast to the 400 V primary switch rating that would be required inan application using a single input cell.

Referring to FIG. 12, an auto-ranging off-line power supply topology isshown including a full-wave rectifier (in this case a bridge rectifier)501, an auto-ranging converter module (“ACM”) 400, and a power regulatormodule 509. The ACM 400, which is discussed in more detail below inconnection with FIG. 9, provides auto-ranging, voltage transformation,and isolation and may optionally provide regulation. The voltage, V₂, atthe output of the rectifier 501 is a function of the AC input voltage,V_(IN), and may therefore vary over a large range. For example, inauto-ranging off-line applications the RMS line voltage may vary between85 and 275 VAC, RMS, corresponding to peak rectified line voltages inthe range of 120V to 389V. In another application example, the RMS linevoltage may vary over a narrower range between 100V and 240V. The ACM400 may be configured to transform the relatively high peak rectifiedline voltage, V₂, to a relatively lower voltage, V₃, (e.g. having a peakvalue of 50V) allowing downstream capacitive energy storage, regulation,and PFC to be provided at the lower voltage. Better figure of meritswitches may be used in the PFC and regulation circuitry while energystorage at the lower voltage may be safer.

Referring to FIG. 9, an integrated VTM array is shown adapted to providethe ACM functions of off-line auto-ranging voltage transformation andisolation. As shown in the figure, the ACM 400 includes two half-bridgeinput cells 401 and 402 and output cell 403 based upon the SAC convertertopology. Preferably, the input cells may be complementary as discussedabove in connection with FIG. 8. The input cells 401, 402 includeprimary windings 416, 426 magnetically coupled to secondary winding 436.In the embodiment shown, the input cells include a series resonantcircuit including the primary winding and a resonant capacitor 417, 427.Primary switches 414, 415 and 424, 425 drive the resonant circuit withone half of the voltage applied across the cell input terminals 410, 411and 420, 421. Capacitors 418, 419 and 428, 429 are scaled to providefiltering on a time scale that is large relative to the resonantfrequency and small relative to the line frequency. Alternatively,full-bridge topologies may be used, eliminating capacitors 418, 419 and428, 429 and replacing them with switches. Output circuitry 430connected to the secondary winding 436 rectifies the secondary voltageand supplies a DC output voltage V0 for delivery to a load (not shown).A switching control circuit 405 operates the primary switches in aseries of converter operating cycles using gate drive transformers 412,413, and 422, 423 to turn the primary switches ON and OFF. Power for theswitching control circuit, at a relatively low voltage, V_(BIAS), may bederived from the input voltage, V_(IN), through an auxiliary windingcoupled to the input cells.

A configuration controller 404 is used to connect the input cells 410,402 in a series and a parallel configuration to provide an auto-rangingfunction. A gate bias voltage is supplied from the gate drivetransformer 422 of input cell 402 through diode 452. The gate biasvoltage is sufficient, e.g. several volts, to ensure that transistor 424is pulsed ON fully. As shown the gate bias voltage is referenced to thesource of transistor 424. When transistor 424 is ON, its source terminalis essentially tied to the positive input terminal 420 causing the gatebias voltage to be referenced to the positive input terminal 420 ofinput cell 402. Terminal 420 will be essentially at V_(IN) for theparallel connection and at V_(IN)/2 for the series connection. The gatebias voltage will provide sufficient drive to transistor 447 to ensurethat it is fully ON in the parallel configuration.

With a sufficiently large positive voltage V_(cont) applied to thecontrol terminal 440, transistor 442 is OFF and transistor 441 is ON,driving the gate of transistor 444 positive and turning transistor 44ON. Transistor 441 pulls the base of transistor 448 and the gate ofp-channel MOSFET transistor 446 low, turning transistor 448 OFF andtransistor 4460N. With the gate bias voltage several volts above inputterminal 420 and with transistor 446 ON, the gate of transistor 447 isdriven above the source of transistor 447 turning it ON. Withtransistors 444, 446, and 447 ON, the input cells are connected inparallel across the input voltage, Vin. The parallel connection of theinput cells allows each cell to share in the power delivered by theoutput cell 403 reducing the current carried by the primary switches.

While the voltage at the control terminal 440 remains below apredetermined threshold (e.g., below a value that causes the gatevoltage of transistor 444 to drop below its gate threshold voltage),transistor 442 remains ON and transistor 441 remains OFF; transistor 448turns ON holding the gate to source voltage of transistor 446 near zerokeeping transistor 446 OFF. With transistors 446 and 444 OFF, transistor447 will be OFF. With transistors 444, 446, and 447 OFF, the input cellsare connected in series (through diode 445) across the input voltage,Vin. The series connection of the input cells divides the input voltagebetween the input cells reducing the voltage requirements of the primaryswitches.

Preferably, the peak line voltage may be sensed and used to set andlatch the control signal V_(cont) to prevent the integrated VTM arrayfrom reconfiguring the input cells as the voltage changes throughout theAC cycle. Alternatively, the configuration may be switched during the ACcycle for example when more than 2 input cells are provided. Circuitryfor sensing the peak line voltage and delivering control signal V_(cont)may be included in switching control circuit 405.

Although the ACM of FIG. 9 is shown using an integrated VTM array basedupon the SAC topology, an ACM comprising an integrated converter arraybased upon other VTM or hybrid VTM-regulating topologies (e.g., PWM VTMsand PWM regulators) may also be used. For example, an integrated VTMarray based upon a hard-switching PWM VTM topology having 2 input cells,an output cell, and a common transformer may be realized by omitting theresonant capacitors 417, 427 in FIG. 9. Alternatively, an ACM withregulation may be may realized using an integrated DC-DC converter arrayin which two or more primary cells are coupled through a commontransformer to an output circuit. Although there may be an efficiencyand EMI penalty as compared to the SAC topology, the integratedhard-switching PWM VTM array and the integrated DC-DC converter arraymay still provide some of the benefits of reduced voltage and currentstresses on the primary switches.

In FIG. 12, the power regulator module (“PRM”) connected to the outputof the ACM 400 provides regulation for the power delivered to the load505. Because the peak input voltage to the PRM is relatively low e.g.,below 50 volts, and varies over a relatively narrow range, e.g. +/−25%,the PRM may use low voltage switches providing a higher figure of meritdue to lower ON resistances and reduced gate capacitance. Because theACM provides isolation, the PRM is preferably non-isolated, thusallowing further improvement in power density. Whereas a capacitivevoltage doubler requires two bulk storage capacitors, only a single bulkstorage capacitor, at the output of the PRM, is required in a systemusing an auto-ranging ACM. Additionally, for ACMs based upon a VTMarchitecture, the PRM may provide PFC (e.g., by controlling the PRM sothat its input current approximately follows the sinusoidal waveform ofthe rectified input source) at a relatively low voltage, for examplebelow 50 Volts, instead of at 400 Volts, as is typical in off-linesystems. Because the energy density of commercially available filtercapacitors rated at 50 volts and 400 volts are comparable, storingenergy at the lower, isolated, voltage provides greater safety withvirtually no impact on power density. In very low voltage applications,the auto-ranging VTM may step the line voltage down to 3-5 Volts andsuper capacitors may be used for energy storage. Although PFC may notgenerally be required in low power (e.g., less than 200 watt) systems,it may be provided in the ACM topology without the size and costpenalties of prior art systems.

In a preferred embodiment, an ACM may be operated over a total AC inputline range of 80 VAC RMS to 275 VAC RMS (corresponding, e.g., tooperating off both a nominal 110 VAC RMS line that varies over a lowinput line range from 80 VAC RMS to 138 VAC RMS, and a nominal 220 VACRMS line that varies over a high input line range from 160 VAC RMS to275 VAC RMS). When operating from the low input line range, the peakrectified voltage at the input to the ACM may vary over a range from 113V PEAK to 195 V PEAK; when operating from the high input line range, thepeak rectified voltage at the input to the ACM may vary over a rangefrom 226 V PEAK to 388 V PEAK. Each of the input cells 410, 402 may havea K factor of 4. When the input cells are configured in series, theeffective K factor will be 8; when the input cells are configured inparallel the effective K factor will be 4.

The “switchover threshold” of such an ACM may be set to be in thenominal center of the range of peak voltages, e.g. at 250 V PEAK. Whenoperating from the low input line range, the peak rectified voltage atthe input to the ACM will be lower than the switchover threshold, thecontrol signal V_(cont) will be set high, the input cells 401, 402 willbe in parallel, the effective K factor will be 4 and the peak voltage atthe output of the ACM will vary over a range between 28.3 VPEAK and 48.8VPEAK; when operating from the high input line range, the peak rectifiedvoltage at the input to the ACM will be higher than the switchoverthreshold, the control signal V_(cont) will be set low, the input cells401, 402 will be in series, the effective K factor will be 8 and thepeak voltage at the output of the ACM will vary over a range between28.3 VPEAK and 48.5 VPEAK. As a result, as the rectified input voltageto the ACM varies between 113 V PEAK and 388 V PEAK, the output of theACM will deliver a voltage that varies approximately +/−27% about anominal peak voltage of 38.5 V PEAK. In many commercial applications,such as AC adapters for notebook computers, the RMS line range isspecified to be narrower (e.g., 100 VAC RMS to 240 VAC RMS), therectified input voltage to the ACM will be narrower and the output ofthe ACM will vary less than +/−27%.

When operated from an AC line, the input to the VTM will be atime-varying waveform that varies between zero volts and the peakvoltage of the AC line, at twice the frequency of the AC line. A VTM isgenerally capable of transforming input voltages essentially down tozero volts, provided that its internal control circuitry remainsoperational throughout the entire rectified line cycle. In preferred ACMembodiments, sufficient holdup (e.g., 10 msec) is provided in theV_(BIAS) supply so that the switching control circuit 405 remainspowered, and capable of driving the ACM switches, even as the rectifiedinput voltage to the ACM goes to zero volts.

The ACM topology may provide even greater power density and savings inthree-phase off-line applications. Referring to FIG. 13, an example ofan ACM delta configuration is shown. Three ACMs 400A-400C are connectedvia full-wave rectifiers 501A-501C between each of the three lines.Although a delta configuration is shown, the system may also beconnected in a star or wye configuration. In either case, the outputs ofthe three ACMs may be connected in parallel to feed a single PRM or aparallel array of PRMs which may also provide PFC. This configurationhas the advantage of maximizing the utility of PRMs increasing the powerdensity even further.

Another embodiment of an auto-ranging off-line power factor correctingpower supply topology 610 is shown in FIG. 14. Similar to the powersupply illustrated in FIG. 12, topology 610 includes a full-waverectifier (e.g. a bridge rectifier) 501, an adaptive VTM array 400, anda PRM 509 with power factor correction. The adaptive VTM array 400,which is discussed in more detail above in connection with FIGS. 9 and12, may provide auto-ranging, voltage transformation, and isolation. ThePRM 509, also discussed above, may provide regulation and power factorcorrection and may preferably use the buck-boost topology described inthe Buck-Boost Patent. The filter capacitor 510 at the output of the PRM509 is required for filtering the pulsating output current of the powerfactor correcting PRM and supplying a DC voltage output to the load 505.

As shown in FIG. 14, the topology 610 additionally includes a hold-upcircuit 612 and hold-up capacitor 650 connected between the VTM array400 and the PRM 509. The hold-up circuit includes switch 615 andparallel unidirectional conducting device 614 in series with theparallel combination of resistance 618 and unidirectional conductingdevice 617. A MOSFET may be used for switch 615 allowing the intrinsicswitch diode to serve as the unidirectional conducting device 614. Asshown, the hold-up circuit provides an asymmetrical path between hold-upcapacitor 650 and the bus voltage V₃. The hold-up circuit may include acontroller 616 for operating switch 615.

The hold-up circuit 612 is used to store energy in the hold-up capacitor650 by charging the capacitor during certain conditions e.g., normalline and load levels, and to supply power from the capacitor to the PRMinput during other conditions e.g., during a line dropout or brownout. Ahigh impedance charging path is provided between the DC bus (voltage V₃)and the hold-up capacitor 650 through unidirectional conducting device614 and resistance 618. While switch 615 is off, the unidirectionalconducting device 614 prevents the capacitor from discharging as thepulsating DC bus voltage V₃ falls back to zero volts during each halfcycle of line frequency. Resistance 618 is set high enough to limit thecharging current to a value that does not exceed the peak currentcapability of the adaptive VTM array 400 (e.g., when the system isinitially turned on or following a hold-up operation). The hold-upcapacitor 650 is charged to the peak value of the pulsating DC busvoltage, V₃.

After the hold-up capacitor 650 is charged to a voltage level sufficientto support the load, it may supply power to the PRM when a hold-upoperation is necessary. When switch 615 is on, a low-impedance dischargepath is provided between the hold-up capacitor 650 and the input of thePRM 509 through unidirectional conducting device 617 and switch 615. Ifa bi-directional topology, such as the SAC topology, is used in theadaptive VTM array 400, reverse power flow from the hold-up capacitor650 to the AC line (V_(in)) is prevented by the input rectifier 501during times when switch 615 is closed. The adaptive VTM may be disabledor the secondary switches in the VTM may be disabled while the hold-upcapacitor supplies power to the PRM.

The hold-up circuit 612 is configured by controller 616 which is used todetect various circuit conditions and to turn switch 6150N (to initiatehold-up operation) and OFF (to terminate hold-up operation). Thecontroller 616 may preferably monitor several voltage levels in thecircuit, including for example, the voltage, V_(H) at the hold-upterminal (to monitor the state of charge of the hold-up capacitor), V₂at the output of rectifier 501 (to determine the line level), V₃ at theoutput of the VTM array (to detect low line conditions), and V_(L) atthe PRM output (to monitor the load regulation). Other levels such asthe PRM output current or load current may be monitored by thecontroller 616 to optimize the hold-up function. Generally, thecontroller 616 will initiate a hold-up operation in response to animminent threat of losing regulation of the load provided that thehold-up capacitor has sufficient charge to support the PRM. An exampleof such an imminent threat includes when the line voltage declines belowthe level required to support PRM operation e.g., during a line dropoutor brownout. The controller 616 may compare the peak value of the busvoltage V₃ to a pre-determined threshold voltage to detect a low-linecondition. Alternatively, the controller 616 may sense an error signalin the PRM regulation circuitry to determine when the PRM is approachingthe limits of its ability to maintain load regulation. As the errormoves to an extreme, such as the rail, a low-line condition may bepresent. The controller 616 generally turns switch 616 OFF terminatingthe hold-up operation either when the threat is removed e.g., the linevoltage returns to within a normal operating range, or when the hold-upcapacitor can no longer support the load i.e., the voltage V_(H) acrossthe hold-up capacitor 650, falls below a predetermined threshold. Amicroprocessor controller may be used to implement the above describedfunctions of the hold-up circuit controller 616 in addition to othercontrol functions such as controlling the power-up and power-downsequences of the power supply 610, including selectively enabling anddisabling the VTM and PRM, controlling PFC in the PRM, and adaptivelyconfiguring the VTM in place of configuration controller 404 in FIG. 9.

As discussed above in connection with FIG. 12, the ACM may optionally beexpanded to include the function of regulation. Accordingly, a preferredimplementation of topology 610 employs a fully integrated powerconversion module, PCM 611, which includes the adaptive VTM array 400,holdup circuit 612, and PRM 509 in a single module as shown by thebroken line in FIG. 14. In the case where the topology provides PFC, thePCM may be called a power factor correction module (“PFM”). The use ofmodule in the PCM and PFM nomenclature refers to a self-containedassembly that is installed as a unit and has terminals for establishingelectrical connections to circuitry external to the module. Therectifier 501, hold-up capacitor 650, and filter capacitor 510preferably are external to the PCM 611 package as discussed in moredetail below.

Referring to FIGS. 19A, 19B, 19C, and 19D, a preferred package 690 forthe module (PCM and PFM) 611 is shown. Package 690 is described in moredetail in Vinciarelli, et al., “Power Converter Package And ThermalManagement,” U.S. patent application Ser. No. 10/303,613, filed Nov. 25,2002 (incorporated here by reference). As shown, terminals 692, e.g.solder balls arranged in a ball grid array, of package 690 provideelectrical connections for the inputs to the VTM array 400, the outputsof the PRM 509, and the hold-up circuitry terminal HU. Additionalterminals may be provided for various other functions in the module.Connectors 691 provide interconnection between module terminals 692 andcontacts 606 on a surface of printed circuit board (“PCB”) 601. Theconnectors 691 are described in more detail in Vinciarelli, et al.,“Surface Mounting A Power Converter,” U.S. patent application Ser. No.10/714,323, filed Nov. 14, 2003 (incorporated here by reference). Asshown in FIG. 19D, connectors 691 allow the module 690 to be surfacemount soldered to PCB 601 via solder connections 602. A 200 W fullyintegrated PCM with PFC for example may be realized in a “Double-VIC”package 690 measuring 32 mm wide by 43 mm long by 6 mm high.

Referring to FIG. 15, another embodiment of an auto-ranging off-linepower factor correcting power supply topology 620 is shown. The topology620, while similar to the topology 610 shown in FIG. 14 in that itcomprises a full-wave rectifier (e.g. a bridge rectifier) 501, anadaptive VTM array 400, a PRM 509 with power factor correction, and alow-line hold-up circuit 622 and hold-up capacitor 650, additionallyincludes a low power boost converter 619 in the hold-up circuit 622.Preferably, the topology 620 employs a fully integrated PCM 621 thatincludes the adaptive VTM array, the hold-up circuit 622, and PRM 509preferably packaged as shown in FIGS. 19A-D. Although the boostconverter 619 is shown included in the hold-up circuit 622, and thusintegrated in the PCM 621, it may also be external to the PCM 621.

The topology 620 also operates in a similar manner to the topology 610in FIG. 14. The hold-up capacitor may be charged through the highimpedance path (unidirectional conducting device 614 and resistance 618)to the peak voltage of the pulsating DC bus, V₃. However, the boostconverter 619 charges the capacitor 650 to a higher voltage to maximizethe energy storage in, and thus optimize the power density of, thehold-up capacitor. The boost converter may preferably be powered fromthe PRM output, instead of the pulsating bus voltage. When thecontroller 616 detects a low line condition, switch 615 is turned ONproviding the low impedance path (via unidirectional conducting device617) from the hold-up capacitor to the input of the PRM 509. Thecontroller 616 further disables the boost converter 619 while thehold-up circuit is providing power to the load.

The boost converter improvement of topology 620 (FIG. 15) supports ahigher power density (discussed more fully below) than is achieved withtopology 610 (FIG. 14) by charging the hold-up capacitor 650 to ahigher, optimum (in terms of power density) voltage level, consistentwith the maximum input operating voltage rating of the PRM. In contrastthe voltage level across the hold-up capacitor in topology 610 (FIG. 14)is dependent on the peak of the pulsating bus voltage, V₃, which varieswith the AC line input voltage. The ratio of the optimum capacitorvoltage to the peak of the pulsating bus voltage at the low end of thenormal line input voltage operating range can be almost 2:1. The boostconverter topological variation (620 in FIG. 15) therefore may allow anincrease in power density by as much as a factor of 4 in the hold-upcapacitor 650, which may be key to maximizing overall system density.

By relaxing the time constant for charging the hold-up capacitor (forexample to 4 seconds or more), the boost converter 619 need process onlya tiny fraction of the power rating of the PRM, allowing the boostconverter 619 to be made small and inexpensive. For a typical example,the hold-up capacitor 650 may be sized so that it can provide holdupenergy, and maintain the PRM input voltage at or above its minimumoperating voltage, for 20 mS, corresponding to approximately 1 cycle ofa 50 Hertz AC line. Using a 4 second charging time constant, the boostconverter need process only about 0.5% (20 mS/4 S=0.005) of the powerwhich the PRM processes. Therefore, in an application in which the PRMis rated to deliver 200 Watts, the boost converter may be a simple ICcapable of delivering 1 Watt peak. Furthermore, the boost converter maybe operated with a low duty cycle because the hold-up capacitor need becharged relatively infrequently.

The space required for a 1 Watt integrated circuit boost converter ismuch less than the space required for an electrolytic capacitor sized toprovide 20 mS hold up at 200 W output power. For example, a typical10,000 uF 50V capacitor (manufactured by Nichicon or Panasonic andavailable in a 1 inch diameter by 2 inch long cylindrical can) chargedto approximately 31 Volts (corresponding to the peak bus voltage with aninput voltage at the low end of the normal input voltage operatingrange) provides barely enough energy storage to provide 20 mS hold up at200 W. Under these conditions, the power density of the hold-upcapacitor is limited to approximately 100 W/in³ which is low relative tothe approximately 400 W/in³ density of the PFM 621. However, by chargingthe same hold-up capacitor to an optimum voltage, e.g. 50V, the powerdensity of the hold up function is cost-effectively boosted to 260 W/in³(more than double compared to the peak charging topology 610). Toachieve even greater hold up density, a battery can be substituted forthe hold up capacitor using a similar boost circuit to maintain thebattery charge.

Referring to FIG. 16, an embodiment of an auto-ranging off-line AC inputpower supply topology 640 is shown. The topology 640 is similar to thetopology 610 in FIG. 14 in that it comprises a full-wave rectifier (e.g.a bridge rectifier) 501, an adaptive VTM array 400, a PRM 509, and alow-line hold-up circuit 642 and hold-up capacitor 650. However,topology 640 differs in that it does not perform PFC and accordingly thefilter capacitance may be moved from the output to the input of the PRMallowing integration of the filter and hold-up functions into a singlehold-up capacitor 650. As with the topologies 610 and 620 of FIGS. 14and 15, the adaptive VTM array 400, hold-up circuit 642, and PRM 509 oftopology 640 may be integrated into a single fully integrated PCM 641 asshown by the broken line in FIG. 16 and packaged as shown in FIGS.19A-D. Like the PFM example above, a 200 W fully integrated PCM withoutPFC for example may also be realized in a “Double-VIC” package measuring32 mm wide by 42 mm long by 6 mm high.

Switch 645 is kept OFF until after the voltage across hold-up capacitor650 reaches a predetermined level to avoid a large in-rush current.During power-up, resistance 648 limits the charge current for capacitor650. Switch 645 is turned ON after the voltage across the hold-upcapacitor reaches the predetermined level and remains ON thereafter.With switch 645 on, the hold up capacitor is charged to the peak voltageduring each line half-cycle. The capacitance 650, which functions as avoltage smoothing filter, may generally be chosen to provide sufficientenergy storage to support the load during low line conditions (asdiscussed above). The controller 646 may turn switch 645 OFF when thevoltage across capacitor 650 falls below a predetermined threshold, inpreparation for another power-on charging cycle. As discussed above,controller 646 functions may be implemented using a microprocessor andmay also include enabling and disabling the PRM and VTM.

Preferably with slight modifications, a DC input connection may beprovided for topologies 610, 620, and 640, allowing the power supply tobe used in many commercial applications in which operation from eitheran AC line or a DC source is desirable, e.g., consumer electronics andnotebook computers. Referring to FIG. 17, topology 660 is shown as ageneralized example of both PFC and non-PFC topologies. Capacitor 510,which is generally necessary for PFC topologies but not required fornon-PFC topologies, is therefore shown in broken lines, the PRM 509,which may or may not provide PFC, omits the with PFC (“w/PFC”) orwithout PFC (“w/o PFC”) labels, and the boost circuit 619 (FIG. 15) isnot shown but may be added to the PFC version of topology 660. In otherwords, the hold-up circuit 662 may be adapted for use in the PFCtopologies 610 and 620, or in the non-PFC topology 640.

As shown, a DC input 647 for connection to an external DC source may beconnected to the hold-up (“HU”) terminal of the hold-up circuit 662. Ahold-up capacitor 650 may also be connected to the HU terminal. Hold-upcircuit 662 differs from the previously discussed hold-up circuits inthe use of a bidirectional switch network including MOSFET switches, 665and 668, connected in series with intrinsic diodes, 664 and 667respectively, poled to block current in both directions. In both PFC andnon-PFC configurations, the inrush current during power up may belimited by switch 665 under control of control circuit 666 thus,possibly, replacing resistance 618 in FIGS. 14-15 or resistance 648 inFIG. 16. A resistance 648 (shown in broken lines) optionally may beprovided to carry some or all of the charging current. When a low ACline condition or other condition necessitating hold-up energy isdetected in either configuration, the controller may turn ON switches665 and 668 to connect the external DC source or hold-up capacitor tothe PRM input. The hold-up circuits 612 (FIG. 14), 622 (FIGS. 15), and642 (FIG. 16) may be implemented using a bidirectional switch networkfor example as shown in the hold-up circuit 662 of FIG. 17. Thecontroller 666 may derive start up power from either the DC or ACsource. As with the topologies 610, 620, and 640 of FIGS. 14, 15, and16, the adaptive VTM array 400, hold-up circuit 662, and PRM 509 oftopology 660 may be integrated into a single fully integrated PCM or PFM661 as shown in FIG. 17 preferably packaged as shown in FIGS. 19A-D. A200 W fully integrated PCM 661 with or without PFC may also be realizedin a module package as shown in FIGS. 19A-D measuring 32 mm wide by 42mm long by 6 mm high.

In applications requiring an external DC input and a hold-up capacitor,it may be desirable to provide a switched connection between the hold-upcapacitor and the DC input terminal. For example, a unidirectionalconduction device or diode (not shown) may be used to prevent reversecurrent flow from the hold-up terminal to the DC input terminal.Alternatively, in addition to a hold-up circuit and hold-up capacitor, abidirectional switch network (of the type shown in FIG. 17) may be usedto connect the DC input terminal to the DC bus.

Referring to FIG. 18, an off-line power factor correcting power supplytopology 670 is shown with a hold-up circuit 672. Topology 670 is shownas a generalized example for both adaptive and non-adaptive VTMtopologies. Therefore, the VTM 400 is not labeled as “adaptive.” The VTM400 provides voltage transformation and isolation and preferablyprovides for adaptive voltage transformation as well. The PRM 509provides PFC and provides boost power conversion and preferably providesbuck-boost power conversion. Like hold-up circuit 662 (FIG. 17), hold-upcircuit 672 includes a bidirectional hold-up switch comprising switches675 and 678. However, unlike hold-up circuit 662 (FIG. 17), hold-upcircuit 672 also includes a smoothing switch 679 connected between thePRM output and the hold-up terminal HU. Smoothing switch 679 may be aunipolar switch as shown in FIG. 18 with the intrinsic diode poled toconduct current from the hold-up capacitor to the load. Alternatively,smoothing switch 679 may be implemented as a bidirectional switch. Theaddition of smoothing switch 679 allows the hold-up capacitor 650 toalso perform as the smoothing capacitor 510 (which is generallynecessary for PFC topologies). Thus hold-up circuit 672 may be used toeliminate one of the relatively low (as compared to the PFM) powerdensity capacitors 510 or 650 allowing additional increases in overallpower density. Smoothing capacitor 510 is therefore shown in brokenlines in FIG. 18. Because the hold-up capacitor 650 in topology 670 isconnected across the load as a smoothing capacitor, topology 670 is notcompatible with the boost circuit 619 of FIG. 15 and the hold upcapacitor is not charged to voltages greater than the load voltage.

During normal load and line operating conditions and during power up,the hold-up circuitry is configured for “smoothing” the PRM output. Inthe “smoothing” configuration the bidirectional hold-up switch is off,the smoothing switch is ON connecting the hold-up capacitor 650 acrossthe PRM output, and the PRM is configured to perform PFC. Thus thehold-up capacitor 650 functions as the smoothing capacitor 510 for thePRM output. During power up, the PRM provides current limiting tocontrol the inrush current into capacitor 650. During a line drop out orother condition requiring hold-up energy, the hold-up circuit isconfigured for “hold-up.” In the hold-up configuration, the smoothingswitch is turned off, the bidirectional hold-up switch is turned ONconnecting the hold-up capacitor 650 to the PRM input, and the PFCfunction is disabled avoiding a pulsating output and the need for asmoothing capacitor across the PRM output. In the hold-up configuration,the PRM regulates the load voltage boosting the hold-up voltage whichdecays from a starting voltage approximately equal to the load voltageas the capacitor 650 discharges. When the line voltage returns or theother condition is removed, the hold-up circuit may be returned to thesmoothing configuration.

In the event that the capacitor 650 is deeply discharged during thehold-up period, a “recharge transition” configuration may be used toavoid disrupting the load regulation until the capacitor 650 isrecharged to an appropriate level, e.g. a level approximating the loadvoltage or at which the PRM can maintain regulation while the capacitor650 charges. In the re-charge transition configuration, the smoothingswitch may be operated in a linear mode to limit the in-rush currentfrom the PRM output to the capacitor 650. After the appropriate voltagelevel is reached, the smoothing switch may be closed returning to thesmoothing configuration.

Depending upon the relationship between the DC bus voltage and the loadvoltage, the capacitor 650 may be at least partially charged usingeither the hold-up configuration (in which the hold-up switch is on) ora modified hold-up configuration (in which the hold-up switch limitscurrent e.g. as described above) prior to or instead of the rechargetransition configuration discussed above. In either case, care must betaken to prevent the capacitor 650 from being charged to a voltagegreater than the maximum load voltage.

Like controllers 616, 646, and 666 discussed above, controller 676 maymonitor voltages V₃, V_(H) and V_(L) to configure the hold-up circuit(hold-up switches 675 and 678 and smoothing switch 679) and also may beused to configure the PRM (enable/disable the PRM and enable/disable thePFC in the PRM) and the VTM (enable/disable the VTM; configure theadaptive array if used). The controller 676 may also monitor voltage V₂as part of a feed forward control loop. The PFM 671 may also be realizedin package 690 as shown in FIGS. 19A-19D.

The bulk energy storage capacitors in topologies 610, 620, 640, 660, and670 is provided at a low voltage that is isolated from the AC line.Additionally, the PCM topologies do not require substantial energystorage in the module or even near the module. This allows the hold upor smoothing capacitor to be separated from the power conversion moduleto provide breakthrough packaging options. For example, the PCM is sosmall that it may be enclosed within a wall plug. The hold-up capacitoror battery 650 does not need to be near the PCM, is safely isolated fromthe AC line and may be easily enclosed in the electronic equipment forwhich power is being supplied. Using a notebook computer application asan example, the PCM topologies may be used to eliminate the ubiquitousexternal brick AC adapter.

A number of embodiments of the invention have been described.Nevertheless, it will be understood that various modifications may bemade without departing from the spirit and scope of the invention. Forexample, it is not required that resonant capacitances C_(R) andinductances L_(R) be included in each of the SAC input cells, as isshown in FIG. 4; it is only necessary that at least one resonantcapacitance and resonant inductance be provided (see, e.g., theintegrated array of FIG. 6 in which a single resonant capacitance, shownin the uppermost primary cell and labeled C_(R), is used). Although fullbridge cells are shown in FIG. 4, the input cells may comprise any SACconfiguration (e.g., full bridge, half bridge, push-pull). Differenttypes of input cells may be combined in an adaptive array SAC. Forexample, a full-bridge input cell may be adaptively connected in serieswith a half-bridge input cell. Furthermore, power-sharing sub-arrays ofVTMs and/or SACs may be configured in adaptive arrays to provideincreased power capacity. The integrated adaptive array also may be usedin other converter topologies to provide an adjustable transformer turnsratio, which in the case of a VTM provides an adjustable voltagetransformation ratio. Accordingly, other embodiments are within thescope of the following claims.

What is claimed is:
 1. A method of converting power from a source at asource voltage for delivery to a load at a load voltage, where thesource voltage may vary between a high line voltage and a low linevoltage in a normal operating range, comprising: providing DC-DC voltagetransformation and isolation in a first power conversion stage, thefirst stage having a CA input for receiving power from the source and aCA output; providing power regulation in a second power conversion stagehaving a PR input for receiving power from the CA output of the firststage, regulation circuitry, and a PR output for delivering power to theload, the regulation circuitry being adapted to maintain the loadvoltage within a regulation range while the PR input voltage remainswithin a normal operating range; providing a hold-up circuit having acharge path and a discharge path for connection to a hold-upcapacitance, the discharge path providing a low impedance connectionbetween the hold-up capacitance and the PR input for supplying power tothe regulation circuitry, the charge path providing a charge current tocharge the hold-up capacitance; configuring the hold-up circuit tocharge the hold-up capacitance when a first predetermined condition issatisfied and to provide power to the PR input when a secondpredetermined condition is satisfied.
 2. The method of claim 1 whereinthe providing DC-DC voltage transformation and isolation furthercomprises providing an integrated adaptive converter array having afirst input cell and a second input cell, each input cell having arespective number, P_(x), of turns, an output cell having a respectivenumber, S_(x), of turns, magnetic coupling between the turns to form atransformer common to the first and second input cells and the outputcell; and further comprising: configuring the input cells in a parallelconnection for operation at the low line voltage and in a seriesconnection for operation at the high line voltage.
 3. The method ofclaim 1 wherein the providing DC-DC voltage transformation and isolationfurther comprises: providing an array of two or more VTMs, each VTMhaving an input, an output, and a substantially fixed voltagetransformation ratio, K=V_(out)/V_(in), over the normal operating range,where V_(in) is the voltage across the respective VTM input and V_(out)is the voltage across the respective VTM output, and providing isolationbetween its input and its output; and configuring the inputs of the VTMsin a parallel connection for operation at the low line voltage and in aseries connection for operation at the high line voltage.
 4. The methodof claim 1, 2, or 3 further comprising providing circuitry forperforming the method in a self-contained assembly having terminals forconnecting to the CA input, the PR output, and the hold-up circuit, forinstallation as a unit, and providing the hold-up capacitor as acomponent external to the assembly.
 5. The method of claim 1 furthercomprising providing control circuitry adapted to detect the first andsecond predetermined conditions and to configure the hold-up circuit. 6.The method of claim 5 wherein the control circuitry is adapted to detectan error signal from the regulation circuitry and the secondpredetermined condition comprises the error signal being outside apredetermined range.
 7. The method of claim 5 wherein the secondpredetermined condition comprises the source voltage being below a firstpredetermined level and the hold-up capacitor being charged above asecond predetermined level.
 8. The method of claim 1 further comprisingproviding a DC input for receiving power from an external DC sourcedirectly coupled to the second power conversion stage.
 9. The method ofclaim 8 wherein the DC input is connected to the PR input via thedischarge path.
 10. The method of claim 8 wherein the DC input isconnected to the PR input via switch circuitry capable of blockingcurrent flow in both directions when OFF and conducting current in bothdirections when ON; and further comprising turning the switch circuitryON to connect the external DC source to the PR input.
 11. The method ofclaim 5 wherein the hold-up circuit comprises switch circuitry capableof blocking current flow in both directions when OFF and conductingcurrent in both directions when ON; and further comprising controllingthe switch circuitry to provide the charge path and the discharge path.12. The method of claim 5 further comprising providing a switch in thedischarge path for connecting the hold-up capacitance to the PR inputwhen the switch is ON.
 13. The method of claim 12 wherein the hold-upcircuit comprises a current limiting element in the charge path.
 14. Themethod of claim 5, 9, or 12 further comprising providing power factorcorrection in the regulation circuitry and providing a smoothingcapacitance at the PR output.
 15. The method of claim 14 furthercomprising providing a boost circuit having an output connected tocharge the hold-up capacitance.
 16. The method of claim 15 wherein theboost circuit comprises an input connected to the PR output.
 17. Themethod of claim 14 further comprising providing circuitry to switch asingle capacitance between a first configuration and a secondconfiguration wherein the capacitance is connected to the PR output asthe smoothing capacitance in the first configuration and is connected tothe hold-up circuit as the hold-up capacitance in the secondconfiguration.
 18. An apparatus comprising: a first power conversionstage for providing DC-DC voltage transformation and isolation, thefirst power conversion stage having a CA input for receiving power froma source at a source voltage and a CA output in which the source voltagemay vary between a high line voltage and a low line voltage in a normaloperating range; a second power conversion stage for providing powerregulation, the second power conversion stage having a PR input forreceiving power from the CA output of the first power conversion stage,regulation circuitry, and a PR output for delivering power to a load,the regulation circuitry being configured to maintain a load voltagedelivered to the load within a regulation range while the PR inputvoltage remains within a normal operating range; and a hold-up circuithaving a charge path and a discharge path, the discharge path providinga low impedance connection between a hold-up capacitance and the PRinput for supplying power to the second power conversion stage, thecharge path providing a charge current to charge the hold-upcapacitance, in which the hold-up circuit is configured to charge thehold-up capacitance when a first predetermined condition is satisfiedand to provide power to the PR input when a second predeterminedcondition is satisfied.
 19. The apparatus of claim 18 wherein the firstpower conversion stage comprises an integrated adaptive converter arrayhaving a first input cell and a second input cell, each input cellhaving a respective number, Px, of turns, an output cell having arespective number, Sx, of turns, and magnetic coupling between the turnsto form a transformer common to the first and second input cells and theoutput cell.
 20. The apparatus of claim 19 wherein the input cells areconnected in series and adapted to divide the source voltage across thefirst and second input cells.
 21. The apparatus of claim 19, comprisingcontrol circuitry for configuring the input cells in a parallelconnection for operation at a low line voltage and in a seriesconnection for operation at a high line voltage.
 22. The apparatus ofclaim 18 wherein the first power conversion stage comprises an array oftwo or more voltage transformation modules (VTMs), each VTM having aninput, an output, and a substantially fixed voltage transformationratio, K=Vout/Vin, over an operating range, where V_(in) is the voltageacross the respective VTM input and Vout is the voltage across therespective VTM output, and each VTM output is isolated from thecorresponding VTM input.
 23. The apparatus of claim 22 wherein theinputs of the VTMs are connected in series and adapted to divide thesource voltage across the VTM inputs of at least two of the two or moreVTMs.
 24. The apparatus of claim 22, comprising control circuitry forconfiguring the VTMs in a parallel connection for operation at a lowline voltage and in a series connection for operation at a high linevoltage.
 25. The apparatus of claim 18 wherein the first powerconversion stage, the second power conversion stage, and the hold-upcircuit are configured as a self-contained assembly having terminals forconnecting to the CA input, the PR output, and the hold-up circuit, forinstallation as a unit, in which the hold-up capacitor is a componentexternal to the assembly.
 26. The apparatus of claim 18, comprisingcontrol circuitry configured to detect the first and secondpredetermined conditions and to configure the hold-up circuit.
 27. Theapparatus of claim 18, comprising control circuitry configured to detectan error signal from the regulation circuitry, and the secondpredetermined condition comprises the error signal being outside apredetermined range.
 28. The apparatus of claim 18 wherein the secondpredetermined condition comprises the source voltage being below a firstpredetermined level and the hold-up capacitor being charged above asecond predetermined level.
 29. The apparatus of claim 18, comprising aDC input for receiving power from an external DC source directly coupledto the second power conversion stage.
 30. The apparatus of claim 18wherein the DC input is connected to the PR input via the dischargepath.
 31. The apparatus of claim 18 wherein the hold-up circuitcomprises switch circuitry capable of blocking current flow in bothdirections when OFF and conducting current in both directions when ON,and a control circuitry controls the switch circuitry to provide thecharge path and the discharge path.
 32. The apparatus of claim 18,comprising a switch in the discharge path for connecting the hold-upcapacitance to the PR input when the switch is ON.
 33. The apparatus ofclaim 18 wherein the hold-up circuit comprises a current limitingelement in the charge path.
 34. The apparatus of claim 18 wherein thesecond power conversion stage provides power factor correction, and theapparatus comprises a smoothing capacitance at the PR output.
 35. Theapparatus of claim 18, comprising a boost circuit having an outputconnected to charge the hold-up capacitance.
 36. The apparatus of claim35 wherein the boost circuit comprises an input connected to the PRoutput.
 37. The apparatus of claim 18, comprising circuitry to switch asingle capacitance between a first configuration and a secondconfiguration wherein the capacitance is connected to the PR output asthe smoothing capacitance in the first configuration and is connected tothe hold-up circuit as the hold-up capacitance in the secondconfiguration.
 38. A method comprising: operating a power conversionmodule having a first power conversion stage, a second power conversionstage, and a hold-up circuit, including using the first power conversionstage to receive power from a source at a source voltage and provideDC-DC transformation and isolation, in which the source voltage may varybetween a high line voltage and a low line voltage in a normal operatingrange; using the second power conversion stage to deliver power to aload and regulate a load voltage at the load to be within a regulationrange; selectively connecting a single capacitance to (i) an output ofthe second power conversion stage such that the single capacitancefunctions as a smoothing capacitance, or (ii) the hold-up circuit suchthat the single capacitance functions as a hold-up capacitance; and whenthe single capacitance functions as the hold-up capacitance, monitoringwhether a first predetermined condition is satisfied, and charging thehold-up capacitance through a charge path in the hold-up circuit if thefirst predetermined condition is satisfied, and monitoring whether asecond predetermined condition is satisfied, and discharging the hold-upcapacitance through a discharge path in the hold-up circuit if thesecond predetermined condition is satisfied, the discharge pathproviding a low impedance connection between the hold-up capacitance andan input of the second power conversion stage.
 39. The method of claim38 wherein the providing DC-DC voltage transformation and isolationfurther comprises using an integrated adaptive converter array having afirst input cell and a second input cell, each input cell having arespective number, Px, of turns, an output cell having a respectivenumber, Sx, of turns, and magnetic coupling between the turns to form atransformer common to the first and second input cells and the outputcell.
 40. The method of claim 39, comprising configuring the input cellsin a parallel connection for operation at the low line voltage and in aseries connection for operation at the high line voltage.
 41. The methodof claim 38 wherein the providing DC-DC voltage transformation andisolation further comprises using an array of two or more VTMs, each VTMhaving an input, an output, and a substantially fixed voltagetransformation ratio, K=Vout/Vin, over the normal operating range, whereVin is the voltage across the respective VTM input and Vout is thevoltage across the respective VTM output.
 42. The method of claim 41,comprising configuring the inputs of the VTMs in a parallel connectionfor operation at the low line voltage and in a series connection foroperation at the high line voltage.
 43. The method of claim 41,comprising providing isolation between each VTM input and thecorresponding VTM output.
 44. The method of claim 38 further comprisingusing circuitry in a self-contained assembly having terminals forconnecting to an input of the first power conversion stage, the outputof the second power conversion stage, and the hold-up circuit, and usingthe hold-up capacitor as a component external to the assembly.
 45. Themethod of claim 38, comprising using control circuitry to detect thefirst and second predetermined conditions and to configure the hold-upcircuit.
 46. The method of claim 38, comprising using a controlcircuitry to detect an error signal from the second power conversionstage, and wherein the second predetermined condition comprises theerror signal being outside a predetermined range.
 47. The method ofclaim 38 wherein the second predetermined condition comprises the sourcevoltage being below a first predetermined level and the hold-upcapacitor being charged above a second predetermined level.
 48. Themethod of claim 38 further comprising receiving power from an externalDC source, and coupling the external DC source directly to the secondpower conversion stage.
 49. The method of claim 48, comprisingconnecting the external DC source to the input of the second powerconversion stage via the discharge path.
 50. The method of claim 38wherein the hold-up circuit comprises switch circuitry capable ofblocking current flow in both directions when OFF and conducting currentin both directions when ON; and further comprising controlling theswitch circuitry to provide the charge path and the discharge path. 51.The method of claim 38 further comprising using a switch in thedischarge path for connecting the hold-up capacitance to the input ofthe second power conversion stage when the switch is ON.
 52. The methodof claim 38 wherein the hold-up circuit comprises a current limitingelement in the charge path.
 53. The method of claim 38 furthercomprising using the second power conversion stage to provide powerfactor correction and using a smoothing capacitance at the PR output.54. The method of claim 38 further comprising using a boost circuit tocharge the hold-up capacitance.
 55. The method of claim 54, comprisingconnecting an input of the boost circuit to the output of the secondpower conversion stage.
 56. The method of claim 1 in which the hold-upcircuit comprises circuitry in the charge path to allow current toconduct in a single direction when charging the hold-up capacitance andblocking current from flowing in a reverse direction from the hold-upcapacitance through the charge path.
 57. The method of claim 1 whereinthe providing DC-DC voltage transformation and isolation furthercomprises: providing an array of two or more VTMs, each VTM having aninput, an output, and a substantially fixed voltage transformationratio, K=V_(out)/V_(in), over the normal operating range, where V_(in)is the voltage across the respective VTM input and V_(out) is thevoltage across the respective VTM output, and providing isolationbetween its input and its output, the inputs of the VTMs being connectedin series and adapted to divide the source voltage across the VTM inputsof at least two of the two or more VTMs.
 58. The method of claim 1wherein the providing DC-DC voltage transformation and isolation furthercomprises providing an integrated adaptive converter array having afirst input cell and a second input cell, each input cell having arespective number, P_(x), of turns, an output cell having a respectivenumber, S_(x), of turns, magnetic coupling between the turns to form atransformer common to the first and second input cells and the outputcell, the input cells being connected in series and adapted to dividethe source voltage across the first and second input cells.